Field
Integrated circuit processing.
Description of Related Art
Modern integrated circuits use conductive (e.g. metal) interconnect layers to connect the individual devices on a chip and/or to send and/or receive signals external to the device(s). Common types of interconnect layers include copper and copper alloy interconnections (lines) coupled to individual devices, including other interconnections (lines) by interconnections through vias, sometimes referred to as via layers or contact layers. It is not uncommon for an integrated circuit to have multiple levels of interconnections (e.g., five or six levels) separated by dielectric materials.
As these interconnect layers or lines are manufactured at smaller pitches (e.g. narrower and/or closer together) in order to accommodate the need for smaller chips, however, it becomes more and more difficult to properly align the vias with the desired interconnect layer. In particular, during manufacturing, the location of the via edges with respect to the interconnect layer or line it is to contact will have variation (e.g. be misaligned) due to natural manufacturing variation. A via, however, must allow for connection of one interconnect layer to the desired underlying interconnect layer or line without erroneously connecting to a different interconnect layer or line. If the via is misaligned and contacts the wrong metal feature (e.g. an undesirable interconnect layer), the chip may short circuit resulting in degraded electrical performance. One solution to address this issue is to reduce the via size (e.g. making the via narrower). Reducing the via size, however, results in degraded performance (due to higher resistance) and potential reduced yield in via manufacturing.